The MPC973 is a 3.3 V compatible, PLL based clock driver device targeted for high performance CISC or RISC processor based systems.
With output frequencies of up to 125 MHz and skews of 550 ps the MPC973 is ideally suited for most synchronous systems. The device offer twelve low skew outputs plus a feedback and sync output for added flexibility and ease of system implementation.
• Fully Integrated PLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• LQFP Packaging
• 3.3 V VCC
• ± 100ps Typical CycletoCycle Jitter
The MPC973 features an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock edge prior to the coincident edges of the Qa and Qc outputs. The Sync output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies, this allows for very flexible programming of the input reference vs output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a nonbinary factor. The PowerOn Reset ensures proper programming if the frequency select pins are set at power up. If the fselFB2 pin is held high, it may be necessary to apply a reset after powerup to ensure synchronization between the QFB output and the other outputs. The internal poweron reset is designed to provide this function, but with powerup conditions being dependent, it is difficult to guarantee. All other conditions of the
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